A Novel Active Shunt-peaked Mcml Array Multiplier

In this paper, a new architecture for MOS Current Mode Logic (MCML) array multiplier for mixed-signal applications is proposed. The proposed architecture employs active shunt-peaking technique in conventional MCML circuits. The technique of active shunt-peaking offers a way for increasing the speed of MCML gates. The performance of the proposed MCML array multiplier is compared with the conventional one through SPICE simulations by using 0.18μm TSMC CMOS technology parameters. It is found out that the proposed array multiplier shows an improvement of 31 percent in the values of delay parameters in comparison to the conventional MCML design. Key word: Current mode logic, shunt-peaking, array multiplier. accumulate computations. Hence, a multiplier is a key element in such modules. In this work, a high speed realization for an array multiplier for mixed signal applications is proposed. The proposed structure employs active inductors and use shuntpeaking technique to increase the speed of the multiplier. The technique was originally demonstrated for analog and RF applications but it can be easily applied to the design of high-speed MCML gates because of the characteristics mentioned above. The paper begins with a brief introduction to conventional MCML circuits in section II. In the next section III, the technique of active-shunt peaking is explained and is applied to MCML circuits. Section IV proposes the architecture and circuits of the array multiplier. The proposed multiplier is implemented, simulated and the results are discussed in section V. Finally, the paper is concluded in section VI. II. MCML CIRCUITS The conventional MCML circuit is differential in nature. It consists of three main components which include a pull-down network (PDN), a current source and resistive load. The PDN realizes the logic